The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device which is integrated on a large scale for high-speed data access.
Various semiconductor memories are known which can read/write data. A typical example of such a semiconductor memory is a dynamic random-access memory (d-RAM) which comprises a matrix of memory cells each consisting of a transistor and capacitor. The memory capacity of the d-RAM chip has recently increased, and integration of memory cells on the d-RAM chip has improved to, e.g., 64 kbit, 256 kbit.
With the high integration of the d-RAM, it is increasingly difficult to keep data access speed high. This is because, signal transfer delay on each word line increases in accordance with an increase in the memory integration of the d-RAM. When the memory cell number per word line is increased, the chip size is enlarged and the length of each word line is increased. In an extreme case, the length of the word line becomes the maximum possible, i.e., as long as one side of the memory chip. As a result, not only the resistance of the word line but also the capacitance between the wiring layer and the chip substrate are increased, thus preventing high speed signal transfer.
When the word lines are formed of polycrystalline silicon, the delay in the signal transfer is particularly serious. This is because there is a large difference (which cannot be permitted in the normal memory operation) between the signal transfer speed at an end portion (i.e., start end portion) at a driving circuit side of the word line of polycrystalline silicon having a larger resistance than that of a metal layer and that at an end portion (terminal portion) farthest from the driving circuit. In the d-RAM, even if the signal transfer speed at the start end portion of the word line is high, if that at its terminal portion is low, the data access speed of the overall memory is determined by the low signal transfer speed at the terminal portion of the word line. A timing design of the d-RAM must be performed with reference to a portion with the lowest signal transfer speed. Therefore, in the conventional device, improvement in data access speed of a highly integrated d-RAM cannot be satisfactorily achieved.
In order to prevent signal transfer delay in the word line, specific materials having low resistance, e.g., a high melting point metal such as tungsten (W), molybdenum (Mo) or the like can be used as a wiring material. However, a method of manufactured a wiring layer using such a metal (called "MOCVD") has not been fully established and still presents some difficulties in practice. In order to solve the above problem, a so-called "word line divisional driving method" is proposed in which word lines are divided into groups and a driving circuit is provided for each word line group. However, in this method, the circuit configuration of driving circuits is complex and the area of peripheral circuits (including the decoder) is undesirably increased, thus preventing high integration of the d-RAM.